Tesla Rewrites Custom Silicon Specs, Setting AI5 Chip Memory to 96GB for Optimus Production

Tesla has rewritten the memory architecture of its next-generation custom artificial intelligence silicon, settling on 96GB of LPDDR5 memory for the upcoming AI5 processor and reducing AI6 memory to 144GB of LPDDR6. Disclosed by CEO Elon Musk, the rapid specification adjustments pivot away from the originally planned 144GB footprint to insulate Tesla from global DRAM component crunches and secure the massive chip volumes required to manufacture Optimus humanoid robots at scale ahead of automotive deployments.

The 96GB Reversal: Trading Raw Capacity for Manufacturing Volume

Over the first two weeks of October 2026, Tesla silicon specifications underwent volatile adjustments in public view. Originally engineered with 144GB of low-power memory, Musk initially cut the AI5 allocation in half to 72GB to maximize factory yields and avoid memory supplier shortages. However, recognizing that 72GB would force the chip into the lowest-density LPDDR5 configurations, Tesla revised the final target up to 96GB. Musk defended the decision by arguing that inference latency in physical robotics is bottlenecked by memory bandwidth rather than total capacity, noting that Tesla preserved peak memory bandwidth while sharply lowering unit bill-of-materials costs.

Silicon Roadmap & Specification Revisions

• AI5 Memory Finalization: Scaled from 144GB planned down to 72GB, before settling on a 96GB LPDDR5 production configuration.
• AI6 Generation Adjustment: Next-generation AI6 memory reduced by one-third, from 216GB of LPDDR6 down to 144GB.
• Bandwidth Preserved: Peak memory bandwidth held constant to maintain real-time vision and trajectory inference on humanoid hardware.
• Cost & Volume Optimization: Lower memory density unlocks millions of viable silicon packages without competing for scarce server DRAM tiers.
• Dual-Sourced Manufacturing: Prepared for production across Samsung 2nm Taylor, Texas fab and TSMC leading-edge nodes.

Optimus Takes Precedence Over Vehicles in Tesla's 2nm Silicon Queue

The architectural change marks a historic inversion in Tesla hardware priorities. While previous processors like HW3 and HW4 debuted strictly in passenger vehicles before being adapted for secondary workloads, the 2-nanometer AI5 processor is slated to deploy inside Optimus humanoid robots and internal AI training clusters first. Vehicle-grade automotive deployment has shifted toward mid-2027, confirming that autonomous physical robotics now drives Tesla core semiconductor procurement and design tradeoffs.

Chip Profile Sheet