Montage Technology Announces Industry-First Trial Production of CXL 3.2 MXC Chip for AI Data Centers

On August 3, 2026, Montage Technology announced trial production of the industry's first Compute Express Link (CXL) 3.2 Memory Expander Controller (MXC) chip. Designed specifically to solve memory bandwidth and capacity bottlenecks in enterprise AI datacenters, the new chip enables composable memory pooling across server clusters.

Unlocking Composable Memory Architecture for AI Workloads

As large language models and multimodal AI clusters demand massive memory footprints, traditional server memory architectures face physical capacity limits. Montage Technology's CXL 3.2 MXC chip enables high-speed, low-latency memory expansion over PCIe interfaces, allowing CPUs and GPUs to dynamically share and pool memory across server racks without hardware reconfiguration.

Key Technical Features

• CXL 3.2 Specification Compliance: Full compliance with Compute Express Link 3.2 standards supporting fine-grained memory pooling.
• PCIe 6.0 Integration: Delivers double the transfer bandwidth of prior generation CXL 2.0 controllers.
• Reduced Memory Latency: Advanced internal caching and physical layer optimization minimize memory access latency for real-time AI inference.
• Hardware RAS Features: Integrated Reliability, Availability, and Serviceability (RAS) safeguards prevent memory corruption in high-volume enterprise clusters.

Industry Impact and Showcase

Montage Technology is showcasing the CXL 3.2 MXC chip during CXL Mini DevCon and the Future of Memory and Storage (FMS) conference in Santa Clara, California. The trial production phase allows major server OEMs and hyperscale cloud providers to begin testing composable memory systems ahead of commercial volume production.

Product & Event Overview