Marvell Showcases Industry-First 2nm Optical Silicon Demos for AI Data Center Infrastructure

At the European Conference on Optical Communication (ECOC 2026) in Málaga, Spain, Marvell Technology unveiled the industry first live demonstrations of 2-nanometer optical interconnect silicon. Engineered to break throughput and thermal bottlenecks in hyperscale AI data centers, the demonstrations showcase 2nm 400G/lane optical PAM4 transmission, 800G ZR/ZR+ coherent pluggables with integrated MACsec security, and a 102.4 Tbps co-packaged optics (CPO) platform designed to link multi-rack AI accelerator clusters beyond copper distance limits.

2nm Optical PAM4 and Coherent DSP Architectures

As artificial intelligence clusters expand across thousands of GPUs, traditional copper interconnects suffer from signal attenuation and excessive power consumption. Marvell latest 2nm silicon demonstrations address this scaling challenge by achieving 400 Gbps per-lane optical PAM4 modulation. Powered by the Marvell Libra 2nm coherent DSP, the company also exhibited live 800G ZR/ZR+ OSFP pluggables featuring integrated hardware-level Media Access Control Security (MACsec), delivering low-latency encryption and dense multi-terabit bandwidth for cloud-scale campus networks.

Key Silicon & Optical Highlights

• First 2nm 400G/Lane PAM4 Demo: Ultra-dense optical signaling designed to accelerate hyperscale transition to 3.2T data center fabrics.
• 2nm 800G ZR/ZR+ with MACsec: Integrates line-rate encryption inside OSFP pluggable transceivers using the Marvell Libra 2nm coherent DSP.
• First 2nm 1.6T Coherent-Lite O-Band: High-efficiency optical DSP architecture delivering high-bandwidth inter-facility and intra-datacenter data transport.
• 102.4 Tbps Co-Packaged Optics Platform: Couples 200G-per-lane silicon photonics directly with switch and AI accelerator compute packages.
• Substantial Energy Reduction: Migrating optical DSP logic to 2nm delivers significant per-bit energy reductions over previous 3nm and 5nm nodes.

Breaking Copper Reach Limits with 102.4T Co-Packaged Optics

A centerpiece of Marvell ECOC showcase is its 102.4 Tbps co-packaged optics (CPO) platform. By co-packaging silicon photonics engines directly alongside host AI accelerators and packet switches, the platform bypasses lossy electrical circuit traces on printed circuit boards. This architectural shift enables hyperscalers to deploy disaggregated AI compute pods spanning dozens of server racks with uncompressed bandwidth density and dramatically reduced cooling requirements.

Technology Profile Sheet